Flagship FPGA resources,
in your hands.
Quad-channel DDR4, PCIe Gen4 and dual 100G links are already routed, impedance-tuned and burn-in tested. You write the logic, not the board.
Browse by form factor
Dev boards, SOMs, FMC mezzanines — from prototype to production.
Development Kits
Full-board delivery, JTAG power-on ready, with reference project and schematics.
System on Module
All IOs on board-to-board connectors; embed into your carrier to shorten the cycle.
FMC Daughter Cards
VITA 57.1 HPC mezzanines for high-speed acquisition, optical and storage extension.
Accessories
Download cables, thermal assemblies, high-speed cables and adapters.
Featured this quarter
In-stock first, complete document packs, sample loan before volume order.
Selection matrix
Check resources and I/O first, then package, power and supply.
| Part | Device | Logic cells | BRAM | High-speed I/O | Supply | Price |
|---|---|---|---|---|---|---|
| PB-VU13P-DEV XCVU13P flagship dev kit |
AMD XCVU13P-2FFGA2104 | 3,780K | 94.5 | PCIe Gen4 x16 / 100G ×2 / FMC HPC | In stock | $4,139 |
| PBCKU15P PBCKU15P核心板 |
XCKU15P-2FFVE1517I | In stock | ||||
| PB-KU060-DEV XCKU060 acquisition dev kit |
AMD XCKU060-2FFVA1156 | 725K | 38 | PCIe Gen3 x8 / FMC HPC / DDR4 | In stock | $1,194 |
| PB-A7-200T Artix-7 XC7A200T dev kit |
AMD XC7A200T-2FBG484 | 215K | 13.1 | GbE / HDMI / ADC | In stock | $372 |
| PB-ZU15EG-DEV Zynq UltraScale+ ZU15EG dev kit |
AMD XCZU15EG-2FFVB1156 | 747K | 26.2 | PS+PL / PCIe Gen3 / Vitis AI | Lead time | $1,736 |
| PB-VU13P-SOM XCVU13P system-on-module |
AMD XCVU13P-2FFGA2104 | 3,780K | 94.5 | Board-to-board / DDR4 ×4 / High-speed connector | Lead time | $3,306 |
| PB-ZU3EG-SOM Zynq UltraScale+ ZU3EG SOM |
AMD XCZU3EG-1SFVC784 | 154K | 7.6 | Small form factor / PS+PL / Stamp hole | In stock | $444 |
Typical use cases
Board + mezzanine + reference design, ready to start.
Radar & array signal processing
Multi-channel synchronous acquisition feeding FPGA pulse compression and beamforming; PCIe to host for display and storage.
Machine vision & real-time inspection
MIPI cameras feed PL for denoise and feature extraction; PS runs lightweight inference, end-to-end latency in ms.
High-speed networking & protocol offload
Dual 100G line-rate capture, PTP timing, traffic analysis and custom protocol offload on FPGA.
Documents are part of delivery, not an afterthought
Every board ships with manual, schematics, pin constraints, reference design and test reports; SOMs also include carrier design guide and impedance conclusions. Document packs follow a unified folder tree and can be synced by script.
Go to support center- Hardware user manual
- Schematics PDF
- XDC pin constraints
- Reference design source
- IBIS & stackup
- Burn-in test report
- Carrier design guide
- Thermal reference design
News
Test reports, firmware updates and supply changes.
Document pack restructured; XDC and IBIS added
The delivery document pack has been restructured. XDC pin constraint f…
Open toolchain support: yosys + nextpnr adaptation notes
We have added yosys + nextpnr adaptation notes for open toolchain user…
Industrial-grade variants (−40 °C to 85 °C) now open for order
Industrial-grade variants (−40 °C to 85 °C) for the PB-VU13P-DEV and K…